DFT Engineer (M, F, D)

## Responsibilities - You will create DFT specifications, create verification plans, and define the SoC test interface. - You will develop and implement the DFT architecture and own its integration into large SoC blocks — including IP integration, system and control bus connectivity, and the integration of memories and hard macros. - You will implement testbenches, generate directed and constrained-random tests, debug failures, run gate-level simulations, and close coverage. - You will also generate structural test vectors, run synthesis and timing closure and work closely with Chip Architecture, DV, Physical Design, and Power teams to achieve first-tapeout success. - Additional responsibilities include supporting STA, physical, power, and logical analysis for DFT modes, partnering with Test Engineers to bring up test vectors on silicon. ## Minimum Qualifications - B.Sc./M.Sc./PhD in Electrical Engineering, Computer Science, or a related field. - Solid knowledge of industry-standard DFT practices, including ATPG, JTAG, MBIST, and the trade-offs between test quality and test time. - Proficient in Verilog and/or VHDL, with hands-on experience using simulators and waveform debugging tools. - Experience developing DFT specifications and driving DFT architecture and methods for designs. - Proven understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon. - Proficient in a scripting language such as Python, TCL, or Perl, including familiarity or proficiency in leveraging generative AI tools to accelerate scripting and engineering workflows. - Ability to fluently speak and write in English, including expressing complex technical concepts clearly. ## Preferred Qualifications - Experience developing DFT specifications and driving DFT architecture and methods for designs - Proven Understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon - Experience debugging compressed ATPG patterns, MBIST, and JTAG/1500 related issues. - Experience with STA constraints development and analysis for DFT modes, as well as SDF simulations. - Ability to conduct experiments during silicon debug, gathering and analyzing data, and using scripting to support efficient handling of ATE data. - Excellent problem-solving and communication skills. - Experience in large SoC design or verification.